 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| \ CDB5451-1 CDB5451-1 Evaluation Board and Software Features l Direct General Description The CDB5451-1 is an inexpensive tool designed to evaluate the functionality and performance of the CS5451. The CS5451 Data Sheet is required in conjunction with the CDB5451 Evaluation Board. The CDB5451-1 Evaluation Board requires use of a CDBCapture+ Board (also available from Cirrus Logic). The CDB5451-1 includes a voltage reference, a digital level-shifter for interface to the CDBCAPTURE+ Board, and voltage regulator which allows for optional +5 V supply operation. The CDBCAPTURE+ accepts the serial output data from the evaluation board and communicates this to the PC via the firmware, enabling quick and easy access to the CS5451 output. The CDB5451-1 includes PC software, allowing the user to perform for data capture (includes option for time domain analysis, histogram analysis, and frequency domain analysis). Real-Time RMS calculation/analysis can be performed on one voltage/current channel pair at a time. ORDERING INFORMATION CDB5451-1 Evaluation Board Shunt Sensor and Current Transformer Interface for 3-Phase Power l On-board Voltage Reference l Supported by CDBCAPTURE+ - RS-232 Serial Communication with PC l Lab Windows/CVITM Evaluation Software - "Real-Time" RMS calculation FFT Analysis Time Domain Analysis Noise Histogram Analysis VA- VA+ +5 VIN GND VD+ Change Pump Circuitry 3V Regulator Control Switches RS232 Cable J18 VIN1+ VIN1IIN1+ IIN1VIN2+ VIN2IIN2+ IIN2VIN3+ VIN3IIN3+ IIN3- CPD VAVA+ GAIN OWRS SE RESET FSO SDO CLK IBM Compatible PC Reset Circuit CDBCapture + CS5451 Crystal 4.000 MHz IN VREF OUT VREF Voltage Reference Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved) AUG `00 DS458DB1A2 1 CDB5451-1 TABLE OF CONTENTS 1. INTRODUCTION........................................................................................................................ 4 1.1 CS5451 .............................................................................................................................. 4 1.2 Data Flow on Evaluation Board ......................................................................................... 4 2. HARDWARE .............................................................................................................................. 5 2.1 Evaluation Board Description............................................................................................. 5 2.2 Connecting the Boards ...................................................................................................... 5 2.3 Power Supply Connections................................................................................................ 6 2.3.1 Analog Power Supply ............................................................................................... 6 2.3.2 Digital Power Supply ................................................................................................ 7 2.3.3 Charge Pump Options.............................................................................................. 7 2.4 Eval Board Control - Headers/Switches............................................................................. 7 2.4.1 Analog Inputs ........................................................................................................... 9 2.4.2 Voltage Reference Input........................................................................................... 9 2.4.3 Clock Source for XIN................................................................................................ 9 2.4.4 S1 DIP Switch .......................................................................................................... 9 2.4.5 Reset Circuit........................................................................................................... 10 3. SOFTWARE............................................................................................................................. 14 3.1 Installing the Software...................................................................................................... 14 3.2 Running the Software ...................................................................................................... 14 3.2.1 Getting Started ....................................................................................................... 14 3.2.2 Selecting a COM Port............................................................................................. 14 3.2.3 Resetting the Boards .............................................................................................. 15 3.2.4 The Data Panel ...................................................................................................... 15 3.2.5 Capture Mode......................................................................................................... 15 3.2.6 Real-Time Mode..................................................................................................... 19 4. ADDENDUM ............................................................................................................................ 24 4.1 Errata for CDBCAPTURE+ .............................................................................................. 24 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ IBM, AT and PS/2 are trademarks of International Business Machines Corporation. Windows is a trademark of Microsoft Corporation. Lab Windows and CVI are trademarks of National Instruments. SPITM is a trademark of Motorola. MicrowireTM is a trademark of National Semiconductor. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS458DB1A2 CDB5451-1 LIST OF FIGURES Figure 1. Connection Diagram ................................................................................................ 5 Figure 2. Power Supply, CS5451, and Oscillator .................................................................. 11 Figure 3. Analog Inputs ......................................................................................................... 12 Figure 4. Digital Circuitry ....................................................................................................... 13 Figure 5. Start-Up Panel ....................................................................................................... 15 Figure 6. Data Panel ............................................................................................................. 16 Figure 7. Silkscreen .............................................................................................................. 21 Figure 8. Circuit Side ............................................................................................................ 22 Figure 9. Solder Side ............................................................................................................ 23 Figure 10.Recent ECO to CDBCapture+ Board .................................................................... 24 DS458DB1A2 3 CDB5451-1 1. INTRODUCTION The CDB5451-1 Evaluation Board operates in conjunction with the Cirrus Logic CDBCAPTURE+ Board. The CS5451, CDB5451-1, and CDBCAPTURE+ data sheets should be read thoroughly and understood before using the CDB5451-1 Evaluation Board. The CDB5451-1 evaluation board provides a quick means of evaluating the CS5451. The CDB5451-1 interfaces to the CDBCAPTURE+ board. The CDBCAPTURE+ board then interfaces to an IBMTM compatible PC via an RS-232 interface. Analysis software supplied with the CDB5451-1 provides a means to display the performance of the CS5451 in the time domain or frequency domain. GAIN = 20). The voltage channel has only the x1 gain setting, and so the input levels on the voltage channel range is +/-800 mV DC. Additional features of CS5451 include a charge pump driver, on-chip 1.2 V reference, and a digital input that can select between two different output word rates. (The two output word rates are equal to XIN/2048 and XIN/1024.) The CS5451 requires a 1.2 V reference input on VREFIN. The modulators and high rate digital filters allow the user to measure instantaneous voltage and current at an output word rate of 3906 Hz (or 1953 Hz, depending on the state of the OWRS pin) when a 4.000 MHz clock source is used. 1.2 Data Flow on Evaluation Board The serial data from the CS5451 is sent through the 10-pin ribbon cable to the CDBCAPTURE+ Board. The data is shifted into parallel format by the CDBCAPTURE+ board, and is stored into SRAM memory. Calculations may be performed on the data before it is sent to the PC via the RS-232 cable, where it can be displayed on the LabWindows screens for viewing. The software interface includes options for viewing a time-domain representation of the sampled waveform, from any one of the six A/D channels. Assuming that the number of samples taken is a whole-number power of 2, an FFT can be performed on the samples for spectral analysis. Histogram analysis can also be performed. The program also has an option to run a real-time rms calculation on one of the three voltage-/current-channel pairs. The resulting energy over each `computation cycle' is also calculated. These results may be saved to file by the user, to allow for additional performance analysis and/or data processing. 1.1 CS5451 The CS5451 is a highly integrated six-channel Delta-Sigma Analog-to-Digital Converter (ADC) developed for the Power Metering Industry. The CS5451 combines six delta-sigma modulators with decimation filters, along with a master-mode serial interface on a single chip device. The CS5451 was designed with the intention of being able to perform as the A/D converter and analog front-end of a 3-phase power metering system. The six ADC channels can be thought of as three pairs of voltage/current-channel ADC's in a digital 3-phase power metering system. However the CS5451 has other potential uses, particularly in motor/servo control applications which require very high precision. The CS5451 contains one three-channel programmable gain amplifier (PGA) for the three current input channels. The PGA sets the maximum input levels of the all three current channels at +/800 mV DC (for GAIN = 1) or +/-40 mV DC (for 4 DS458DB1A2 CDB5451-1 2. HARDWARE 2.1 Evaluation Board Description The CDB5451-1 board supplies power to the CS5451, provides six channels of analog input, and provides the six-channel A/D serial output data for further analysis. All of the actual data manipulation and calculations are performed by the DSP on the CDBCAPTURE+ Board, and by the LabWindows software. The following discussion introduces the various sections of the board. 2.2 Connecting the Boards Three different cables are needed. The CDB54511 comes shipped with one cable: a 20-pin ribbon bus cable. The user should also have one RS-232 cable and one 10-pin ribbon bus cable that are supplied with the CDBCAPTURE+ board. A simple connection diagram is shown in Figure 1. The evaluation board interfaces to the CDBCAPTURE+ board through a 10-pin bus cable, as well as through a 20-pin bus cable. The user must make CDB5461 Evaluation Board J17 HDR16 10-pin Ribbon Cable J18 20-pin Ribbon Cable RS232 Cable IBM Compatible PC HDR1 CDBCapture + Figure 1. Connection Diagram DS458DB1A2 5 CDB5451-1 sure that these cables are connected to the boards in the correct orientation. Referring to Figure 1, first attach the 10-pin bus cable to "HDR1" on the CDBCAPTURE+ board such that the ribbon is extending away from the edge of the board. Connect the other end of this cable to "HDR16" on the CDB5451-1 board. Again make sure that the ribbon is extending outward from the CDB5451-1 board. Next connect the 20pin ribbon cable to "J18" on the CDBCAPTURE+ board, and connect the other end to "J17" on the CDB5451-1 board. Again, for both connections, make sure that the cable leads extend outward, away from the board. Finally, the RS-232 cable is shown connecting the CDBCAPTURE+ Board to the user's PC. The user should connect the RS-232 cable to an available COM port on the PC. 2.3 Power Supply Connections The CDB5451-1 can be used in several different power supply configurations. Table 1 shows the various possible power connections with the required jumper settings. There are various +3 V and +5 V options. 2.3.1 Analog Power Supply Referring to Figure 2, the A+ post supplies power to the positive analog power input pin (VA+) of the CS5451. This post also supplies power to the LT1004 voltage reference (D3) and the optional Power Supplies Analog +3 +3 +3 +3 +3 +3 +3 +3 +3 +3 +5 Digital +3 +3 +3 +3 +3 +3 +5 +5 +5 +5 +3 A+ +3 +3 +3 +3 NC NC +3 +3 NC NC +5 Power Post Connections A-2 -2 NC NC -2 NC -2 NC -2 NC 0 GND 0 0 0 0 0 0 0 0 0 0 +2 D+ +3 NC +3 NC NC NC +5 +5 +5 +5 +5 +5 V NC NC NC NC +5 +5 NC NC +5 +5 NC HDR9 A- O O CPD O O A- O O CPD O O AO CPD O AO CPD O O O O O HDR17 +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O +5V_IN O O A+ +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O +5V_IN O A+ O O O O O O O O O O O O O O O O O O O O O O O HDR18 VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O VD+ O V+ O O O O O O O O O O O O O O O O O O O O O O O A- O O CPD O O AO CPD O O O A- O O CPD O O AO CPD O O O A- O O CPD O O AO CPD O O O A- O O CPD O O Table 1. Power Supply Connections 6 DS458DB1A2 CDB5451-1 +3V regulator (U5). If HDR9 is set to the "A-" setting, the A- post can supply the required negative voltage to the VA- pin of the CS5451. Note that the evaluation board is equipped with a LM317 voltage regulator (U5), set to create +3 V from a +5 V supply. This option is useful if the user has only one power supply which must be used to power both the CDBCAPTURE+ and CDB5451-1 board. With HDR17 set to "+5V_IN", one single +5 V supply can be used to provide both the +5 V power for the CDBCAPTURE+ Board, as well as +3 V for the CDB5451-1 board. 2.3.3 Charge Pump Options The output from CS5451's charge-pump driver pin (CPD) can be used to generate a -2V supply when the proper jumper settings are selected. The -2 V can be used as the negative power supply connection to the VA- pin. Referring to Figure 2, circuitry for a charge-pump circuit is included on-board. The charge pump circuit consists of capacitors C11, C12, and C36, and diodes D1 and D2. As an alternative to using the charge pump circuit, the user can supply an off-board -2V DC power source to the "A-" banana connector. This option is controlled by switching HDR9. 2.3.2 Digital Power Supply The A+ post can be used to supply both the analog power (to CS5451 VA+ pin) as well as the digital power (to CS5451 VD+ pin). However if a separate supply voltage is desired for the digital power supply, the "VD+" banana connector post can be used to independently supply digital power to the input of the CS5451 (VD+ pin), the 4.000 MHz oscillator (U1), and tri-state buffer (U3). This is controlled by setting on HDR18. Name HDR1 Function Description 2.4 Eval Board Control - Headers/Switches Table 2 lists the various adjustable headers and switches on the CDB5451-1 Evaluation Board, as well as their default settings (as shipped from the factory). The header settings can be adjusted by the user to select various options on the evaluation board. Default Setting IIN3+ Set to BNC J2 Default Jumpers O O O IIN3+ O AGND Used to switch IIN3+ on the CS5451 between J2 and AGND. Used to switch VIN3- on the CS5451 between J3 and AGND. Used to switch VIN3+ on the CS5451 between J1 and AGND. Used to switch IIN3- on the CS5451 between J4 and AGND. Used to switch VIN2- on the CS5451 between J6 and AGND. Used to switch IIN2+ on the CS5451 between J7 and AGND. HDR2 VIN3- Set to BNC J3 O O O VIN3O AGND HDR3 VIN3- Set to BNC J1 O O O VIN3+ O AGND HDR4 IIN3- Set to BNC J4 O O O IIN3O AGND HDR5 VIN2- Set to BNC J6 O O O VIN2O AGND HDR6 IIN2+ Set to BNC J7 O O O IIN2+ O AGND Table 2. Default Header Settings DS458DB1A2 7 CDB5451-1 Name HDR7 Function Description Used to switch IIN2- on the CS5451 between J5 and AGND. Used to switch VIN2+ on the CS5451 between J8 and AGND. Used to switch between external VA- and on-board CS5451 charge-pump circuit, CPD Used to switch VIN1+ on the CS5451 between J9 and AGND. Used to switch IIN1- on the CS5451 between J12 and AGND. Used to switch IIN1+ on the CS5451 between J10 and AGND. S1 settings valid ONLY when J17 is disconnected Default Setting IIN2+ Set to BNC J5 Default Jumpers O O O IIN2O AGND HDR8 VIN2+ Set to BNC J8 O O O VIN2+ O AGND HDR9 CPD active A- O CPD O O O HDR10 VIN1+ Set to BNC J9 O O O VIN1+ O AGND HDR11 IIN1- Set to BNC J12 O O O IIN1O AGND HDR12 IIN1- Set to BNC J10 1 O O O IIN1+ O AGND S1 S1-1 is used to set CS5451 USE S1-2 is used to set CS5451 UOWRS S1-3 is used to set CS5451 GAIN Used to switch VIN1- on the CS5451 between J11 and AGND. Used to switch the VREFIN from external VREF post connector, to the on board LT1004 reference, or to the on-chip reference VREFOUT. Refer to Table 3. Controls the source for the CS5451 XIN clock input. Used as connector for 10-pin ribbon cable. Determines whether the main analog supply will be powered from the A- post, or from the regulated 3V voltage (generated from the +5V_IN) post input. Choose whether the digital circuitry will be powered by main analog supply, or powered by separate digital supply (through VD+ post). S1-1 Set to Enable S1-2 Set to 1 MHz S1-3 Set to GAIN = 1 2 3 OPEN HDR13 VIN1- Set to BNC J11 VREFIN Set to onchip reference VREFOUT Set to on-board 4.000 MHz crystal (U1). NA Set to ASet to main analog supply O O O VIN1O AGND HDR14 O O O O LT1004 O VREFOUT O EXT VREF HDR15 HDR16 HDR17 O O O O EXT XIN O DGND O 4.00 MHz OSC NA O O O +5V_IN O A+ HDR18 VD+ O V+ O O O Table 2. Default Header Settings (Continued) 8 DS458DB1A2 CDB5451-1 2.4.1 Analog Inputs The settings on the twelve analog input headers (2 per channel) determine which inputs will carry a signal, and which inputs may be grounded. They can be configured to accept either a single-ended or differential signal. Using the voltage channel #1 as an example (see Figure 3) note that HDR10 sets the input to the positive side of the first voltage channel input (VIN1+ pin). HDR13 sets the input to the negative side of the first voltage channel input (VIN1- pin). In a single-ended input configuration, HDR13 would be set to the "AGND" setting, and HDR10 would be set to "VIN1+" and would conduct the single-ended signal. In a differential input configuration, HDR13 would be set to "VIN1-" and HDR10 would be set to "VIN1+" and this pair of inputs would form the differential input pair into the VIN1+ and VIN1- pins of the CS5451. Several patch-circuit areas are provided near the voltage/current input headers, in case the user wants to connect special sensor circuitry to the analog inputs (such as transformers, shunt resistors, etc., for monitoring a 3-phase power line). For each of the three channels, a Shunt Resistor or Current Transformer can be mounted in these areas and connections can be made to the individual currentchannel inputs. Likewise, for each of the three channels, a Voltage Divider or Voltage Transformer can be connected for each of the converter's three voltage inputs. Note from Figure 3 that a simple R-C network filters each sensor's output to reduce any interference picked up by the input leads. The 3 dB corner of the filter is approximately 50 kHz differential and common mode. Other header options listed in Table 2 allow the user to set the source of the input clock signal and the source of the voltage reference (VREFIN) input, etc. The voltage reference options and clock input options are discussed next. 2.4.2 Voltage Reference Input To supply the CS5451 with a suitable 1.2 V voltage reference input at the VREFIN pin, the evaluation board provides three voltage reference options: onchip, on-board, and external. See HDR14 as shown in figure 2. Table 3 illustrates the available voltage reference settings for HDR14. With HDR14's jumpers in position "VREFOUT," the CS5451's on-chip reference provides 1.2 volts. With HDR14 set to position "LT1004," the LT1004 provides 1.23 volts (the LT1004 temperature drift is typically 50 ppm/C). By setting HDR14's jumpers to position "EXT VREF," the user can supply an external voltage reference to J16 connector post (VREF) and AGND inputs. Reference LT1004 Description Selects on board LT1004 Reference (5 ppm/C) Selects reference supplied by CS5451 Selects external reference HDR14 O O O O O O O O O O O O O O O O O O LT1004 VREFOUT EXT VREF LT1004 VREFOUT EXT VREF LT1004 VREFOUT EXT VREF VREFOUT EXTVREF Table 3. Reference Selection 2.4.3 Clock Source for XIN A 4.000 MHz crystal is provided to drive the XIN input of the CS5451. However, the user has the option to provide an external oscillator signal for XIN, by switching the setting of HDR15. 2.4.4 S1 DIP Switch The S1 DIP switch is used if the user wants to remove the 20-pin cable from the CDBCAPTURE+ Board, in an effort to reduce noise from the CDBCAPTURE+ Board that is transferred through the cable. Disconnecting this 20-pin cable would be done only for very low-noise, precision measurements. Slightly higher performance of the CDB5451-1 may be obtained when it is discon9 DS458DB1A2 CDB5451-1 nected. Note that the DIP switch settings on S1 are only valid when the J17 connector is disconnected from the CDB5451-1 board. When J17 is disconnected from CDB5451-1 board, the three switches on S1 independently control the logic levels of the SE pin, the OWRS pin, and the /GAIN pin on the CS5451. But when J17 is connected between the CDB5451-1 board and the CDBCAPTURE+ board, the S1 settings have no effect, and the pin logic levels are controlled instead by manipulating the on-screen switches in the PC software. 2.4.5 Reset Circuit Circuitry has been provided which allows the user to execute a hardware reset on the CS5451. See Figure 4. By pressing on the S2 switch, the /RESET pin on the CS5451 will be held low until the switch is released. 10 DS458DB1A2 100 J21 Z4 P6KE6V8P C42 10UF C39 .1UF C40 .1UF C41 22UF 1 140 R31 R29 1K R30 CON_BANANA HDR17 HDR2X2 3 1 4 2 V+ A+ J14 R2 R3 4.99K TP40 TP1 2 L1 10 FERRITE_BEAD TP40 TP76 GND GND VREFIN VREFOUT VA+ VAVIN3+ VIN3IN3+ IN3- VIN1+ VIN1IIN1+ IIN1VIN2+ VIN2IIN2+ IIN2- J13 1.2V 4 6 3 5 GND D3 LT1004 3 +3V BNC_RA GND 2 HDR2X2 HDR9 4 1 AJ15 Z1 P6KE6V8P C15 47UF C1 .1UF TANT 2.2UF C12 3 DS458DB1A2 U5 CON_BANANA LM317LZ 3 TP40 TP77 2 +5V_IN IN OUT ADJ 3.0V D+ GND V+ HDR18 HDR2X2 1 2 4 GND C38 .33UF TANT U4 SCLK SDO FSO SE /GAIN CON_BANANA CON_BANANA J18 GND GND C20 .1UF VIN3+ VIN3IN3+ IN3- TP36 TP38 TP40 TP42 TP44 TP46 TP48 TP50 TP52 TP54 TP56 TP58 TP60 TP62 4.7UF TANT TP37 TP39 TP41 TP43 TP45 TP47 TP49 TP51 TP53 TP55 TP57 TP59 TP61 TP63 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCLK SDO FSO SE /GAIN AGND VREFIN VREFOUT VA+ VAVIN3+ VIN3IN3+ IN3- VD+ DGND CPD XIN /RESET OWRS VIN1+ VIN1IIN1+ IIN1VIN2+ VIN2IIN2+ IIN2- 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TP79 TP73 TP74 TP14 TP17 TP19 TP21 TP23 TP25 TP27 TP29 TP31 TP33 TP35 TP78 TP72 TP75 TP15 TP16 TP18 TP20 TP22 TP24 TP26 TP28 TP30 TP32 TP34 3 VD+ C21 XIN /RESET OWRS VIN1+ VIN1IIN1+ IIN1VIN2+ VIN2IIN2+ IIN2- C14 C22 .1UF .1UF C23 47UF Z3 J20 P6KE6V8P 10UF GND GND GND +3V GND C37 SSOP28_200_P65MM U2 SCLK SDO FSO SE /GAIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCLK SDO FSO SE /GAIN AGND VD+ DGND CPD XIN /RESET OWRS Z2 P6KE6V8P C13 47UF C17 .1UF HDR3X2 HDR14 2 1 C19 .1UF C16 .1UF TP2 TP40 VIN3+ VIN3IN3+ IN3- 28 27 26 25 24 23 22 21 20 19 18 17 16 15 XIN /RESET OWRS VIN1+ VIN1IIN1+ IIN1VIN2+ VIN2IIN2+ IIN2GND GND EXT_IN CV21AF-4.000MHz CLKOSC C18 .1UF 14 7 GND CON_BANANA GND GND SKT_SSOP28_ENP TANT 4.7UF C36 HDR3X2 HDR15 2 4 6 1 3 5 GND 8 XIN XT VREF J16 C2 .1UF D2 BAT85 C11 .039UF D1 BAT85 D+ R32 10 VCC U1 GND CON_BANANA GND GND GND CDB5451-1 Figure 2. Power Supply, CS5451, and Oscillator 11 1 2 3 4 GND J25 J23 GND .01UF HDR2X2 HDR13 1 3 2 4 GND 1 2 3 4 GND 1 2 3 4 12 J22 1 2 3 4 TP67 J5 BNC_RA R23 301 0.1% C8 4700PF TP66 GND HDR2X2 HDR7 1 3 2 4 IIN2- C24 .01UF J7 BNC_RA R22 301 0.1% GND HDR2X2 HDR6 1 3 2 4 GND IIN2+ C25 .01UF J24 TP65 J6 BNC_RA R21 301 0.1% C7 4700PF TP64 GND HDR2X2 HDR5 1 3 2 4 GND VIN2- 1 2 3 4 C26 J1 TP71 R19 301 0.1% C6 GND HDR2X2 HDR3 1 3 2 4 .01UF HDR2X2 HDR8 1 3 2 4 VIN3+ BNC_RA C32 .01UF J8 BNC_RA GND VIN2+ R24 301 0.1% GND C27 J3 4700PF TP70 R18 301 0.1% GND HDR2X2 HDR2 1 3 2 4 GND VIN3- .01UF BNC_RA C33 .01UF GND TP69 J2 R17 TP4 J12 BNC_RA R26 301 0.1% C9 4700PF TP5 GND HDR2X2 HDR11 1 3 2 4 BNC_RA 301 0.1% C5 4700PF TP68 GND HDR2X2 HDR1 1 3 2 4 GND IN3+ 1 2 3 4 C34 .01UF IIN1- C28 .01UF J4 R20 J10 BNC_RA R27 301 0.1% HDR2X2 HDR12 1 3 2 4 BNC_RA 301 0.1% GND HDR2X2 HDR4 1 3 2 4 GND IN3- GND IIN1+ C35 .01UF C29 J27 GND TP6 J11 BNC_RA GND VIN1- R28 301 0.1% C10 4700PF TP3 GND C30 .01UF J9 BNC_RA R25 301 0.1% GND HDR2X2 HDR10 1 3 2 4 GND VIN1+ C31 .01UF J26 GND CDB5451-1 DS458DB1A2 Figure 3. Analog Inputs R10 R9 GND 10K 10K HDR5X2 HDR16 10K R8 4 6 8 10 3 5 7 9 FSO SCLK SDO SW_DIP_3 OPEN R15 R4 R7 GND .1UF U3 20 C3 GND R6 GND CON10X2_LE J17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10K 10K 10K VCC 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 GND SN74VHC244N 1/G 1A1 1A2 1A3 1A4 2/G 2A1 2A2 2A3 2A4 OWRS /RESET /GAIN SE TP9 TP11 TP13 TP8 TP10 TP12 SCLK FSO 18 16 14 12 1 2 4 6 8 19 11 13 15 17 USCLK UFSO UOWRS USE UOWRS U/GAIN U/RESET U/GAIN USE USCLK UFSO SDO 10 R14 9 7 5 3 TP7 10K GND GND GND C4 .1UF R5 1K R16 D+ 20K R1 10K DS458DB1A2 13 HDR12X2 HDR20 OWRS /RESET /GAIN SE USCLK UFSO USE UOWRS U/GAIN FSO SCLK SDO 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 D+ S1 D+ 2 1 U/GAIN UOWRS USE R11 R12 R13 10K 10K 10K 3 2 1 GND GND D+ D+ GND Figure 4. Digital Circuitry GND CDB5451-1 49.9 S2 SW_B3W_1100 U/RESET GND CDB5451-1 3. SOFTWARE The evaluation software was developed with Lab Windows/CVITM, a software development package from National Instruments. The software is designed to run under Windows 95TM or later, and requires about 3 MB of hard drive space (2 MB for the CVI Run-Time EngineTM, and 1 MB for the evaluation software). After installing the software, read the readme.txt file for any last minute updates or changes. More sophisticated analysis software can be developed by purchasing the development package from National Instruments (512-794-0100). resolution. If the user interface seems to be a little small, the user might consider setting the display settings to 640 x 480. (640x480 was chosen to accommodate a variety of computers). 3.2 Running the Software 3.2.1 Getting Started The CDB5451-1 Evaluation software allows the user to obtain, display, and save data that is acquired by the CS5451 chip. First, connect the CDB5451-1 and CDBCAPTURE+ boards as described in Section 2., "Hardware". Apply power to the boards. To start the software, double click on the EVAL5451 icon, or initiate through the Start menu. 3.1 Installing the Software Installation Procedure: 1) Turn on the PC, running Windows 95TM or later. 2) Insert the Installation Diskette #1 into the PC. 3) Select the Run option from the Start menu. 4) At the prompt, type: A:\SETUP.EXE Note: The software is written to run with 640 x 480 resolution; however, it will work with 1024 x 768 3.2.2 Selecting a COM Port After launching the software, the user will be presented with the "Start-Up" Panel. A picture of the Start-Up Panel is shown in Figure 5. This panel indicates the name and version of the CDB54541 Evaluation Software. Also, a small pop-up dialogue box will appear which prompts the user to select a COM port. To select a COM port, first use the mouse to click on the "OK" button in this dialogue box. Next, use the mouse to click on the menu item "Select" and then choose the appropriate COM port setting (either COM1 or COM2). Note that the COM port settings on the host PC are configured to the following settings: 9600 baud, no parity, 8-bit data, and 1 stop bit. The COM port's Flow Control setting should be set to "Xon / Xoff." These settings should be set automatically by the LabWindows software. (The user may have to set the COM port settings manually if using Windows NT operating system. In this case, the user should run launch a Hyperterminal window to program the COM port settings, then exit Hyperterminal, then run the CDB5451-1 Software.) 14 DS458DB1A2 CDB5451-1 Figure 5. Start-Up Panel 3.2.3 Resetting the Boards After the COM port has been selected a second pop-up dialogue box will appear, to prompt the user to press the reset buttons on the CDB5451-1 board and on the CDBCAPTURE+ board before continuing. The user should follow these instructions: First, press on the button labeled "S2" on the CDB5451-1 board, and then press on the button labeled "S1" on the CDBCAPTURE+ board. Finally, use the mouse to click on the "OK" button to close this dialogue box. At this point, the mouse cursor will turn into the hour-glass shape while certain information is loaded from the PC software into the CDBCAPTURE+ board. This will take about 8 seconds. The user should wait until the mouse cursor has returned to its normal appearance before proceeding. 3.2.4 The Data Panel The Data Panel is where all of the analysis tools are located. See Figure 6. To get to the Data Panel, go to the menu item called "Panel" and select the option called "Data Panel." A new panel will appear on the screen. This is the Data Panel. Once in the data panel, the user has two options available: Capture and Real-Time. 3.2.5 Capture Mode Capture mode allows user to capture waveform data from the CS5451. The data can be ported back to the PC and displayed as a graph. The functionality of each control in the Capture portion of the Data Panel is described below. In order to give the user an idea of the proper sequence of actions that should be taken to perform a data capture, a typical sequence of user-actions is listed below. DS458DB1A2 15 CDB5451-1 Figure 6. Data Panel 3.2.5.1. TYPICAL CAPTURE SEQUENCE: 1) In the Data Panel, select Channel Pairs 1, 2, and/or 3 by switching the switches in the box labelled "Channel-Pair Selector." 2) Press on the button labelled "CAPTURE". Wait until the capture is completed. 3) Determine how many data words should be ported up from the Capture+ Board's memory to the PC. Enter this number in the box labeled "Words" 4) Using the mouse, click on the "SRAM To PC" button. 5) Select one of the channel boxes that indicate the number of samples received. For instance, click inside the "V_2 samples" box (assuming that the Channel 2 Pair was among the pairs that had been selected for capture). 6) Using the mouse, press (click) on the "TIMEPLOT" button to view the sampled data, which shows the A/D conversions from the channel selected in the previous step. 3.2.5.2. DESCRIPTION OF DATA PANEL CONTROLS * "CAPTURE" Capture initiates the data capture sequence. Depending on how many of the three channel pairs are selected, the user may capture data for all three channel pairs, two channel pairs, or just one channel pair (note that each pair represents one voltage channel and one current channel.) The software automatically determines the maximum number of frames that it can store in memory, and then adjusts the number indicaDS458DB1A2 16 CDB5451-1 tor box that reads: "Frames of Data Being Stored." Once the "CAPTURE" button is pressed (by using the mouse) it should turn red-colored, and the mouse cursor should change to an hourglass symbol. The CDBCAPTURE+ will now gather raw data from the CDB5451-1 board, and store the data into its on-board memory. Once the capture process has stopped, then the "CAPTURE" button should turn back to gray color. Now the data is in memory. * "SRAM to PC" After capturing the data (with the "CAPTURE" button), the data must be transferred from the memory on the CAPTURE+ board to the PC. To actually get the data from the CDBCAPTURE+ board up to the PC, the user must now press on the "SRAM to PC" button. Before doing this, the user should observe the value in the number box labelled "Words." The user can change the value in this box. The user should make sure that the number of samples that are going to be brought up will be a `reasonable' number. This mainly applies to the FFT analysis: If the user wants to get meaningful FFT results, the user must make sure that the number of samples loaded for one particular channel will be some whole-number power of 2 (...,8, 16, 32, 64, 128, 256,...). EXAMPLE 1: 1) Capture data for all three channel pairs. This will set the value in the "Frames of Data Being Stored" box to 8192. 2) User can transfer up to 8192 pieces of data for each of the six channels. But suppose user only wants 4096 samples from each channel. Note that 4096 is a power of 2, so this is OK. So multiply 4096 x 6 = 24576. Enter this number into the "Words" box. * EXAMPLE 2: 1) Change the "Channel Pair Selector" buttons to capture data for channel pairs 1 and 3. This represents 4 channels worth of data (each pair has both voltage and current). After mouse-clicking on the "CAPTURE" button, note that the number in the "Frames of Data Being Stored" box changes to 16384. 2) After capture has completed, the user can transfer up to 16384 samples for each of the four channels. If user wants the maximum number of samples possible, multiply 16384 x 4 = 65536. Enter this number into the "Words" box. Then mouse-click on the "SRAM to PC" button. If user wants only 8192 samples, then transfer 8192 x 4 = 32678. Therefore, the user should enter "32678" into the "Words" box. Then use the mouse to click on the "SRAM to PC" button. * "V_1 samples" This box indicates how many channel 1 voltage samples were transferred from the CDBCAPTURE+ board up to the PC. To make channel 1 voltage samples the active data array, just click the mouse once inside this box. Note: The "active data array" indicates which collection of samples is now stored in the array that will be plotted/saved if certain other commands/functions are initiated. For example, after running "SRAM to PC", if the user clicks inside the box called "V_1 samples", then these samples will be loaded in as the active data array.* "I_1 samples" This box indicates how many channel 1 current samples were transferred from the CDBCAPTURE+ board up to the PC. To make channel 1 current samples the active data array, just click inside this box. DS458DB1A2 17 CDB5451-1 * "V_2 samples" This box indicates how many channel 2 voltage samples were transferred from the CDBCAPTURE+ board up to the PC. To make channel 2 voltage samples the active data array, just click inside this box. * "I_2 samples" This box indicates how many channel 2 current samples were transferred from the CDBCAPTURE+ board up to the PC. To make channel 2 current samples the active data array, just click inside this box. * "V_2 samples" This box indicates how many channel 2 voltage samples were transferred from the CDBCAPTURE+ board up to the PC. To make channel 2 voltage samples the active data array, just click inside this box. * "I_2 samples" This box indicates how many channel 2 current samples were transferred from the CDBCAPTURE+ board up to the PC. To make channel 2 current samples the active data array, just click inside this box. * "FFT" Performs an FFT on the active data array and displays it in the graph window. For this function to work correctly, the number of samples in the active data array must be equal to some whole-number power of 2. * "TIMEPLOT" Graphs the samples of the active data array. The x-axis indicates the sample number. The y-axis indicates the coded word values from the CS5451 A/D converter. * "HISTOGRAM" Performs a statistical histogram analysis of the active data array, then plots the results in the 18 graph window. The user can set the number of bins for the histogram in the box called "Number of Bins in Histogram." * "Minimum" This indicator box displays the minimum value of the active data array, after the HISTOGRAM analysis has been run on the active data array. * "Maximum" This indicator box displays the maximum value of the active data array, after the HISTOGRAM analysis has been run on the active data array. * "Mean" This indicator box displays the mean value of the active data array, after the HISTOGRAM analysis has been run on the active data array. * "Sample Freq" This indicator box displays the sampling rate of the CS5451. The CDB5451-1 has two different sampling rates: 3906 Hz and 1953 Hz. These two sampling rates correspond to the logic level of the OWRS pin of the CS5451. See CS5451 data sheet for more details. * "S/N" After the "FFT" function is executed, this indicator box calculates the signal-to-noise ratio with respect to the fundamental of the active data array, after the "FFT" function is executed. * "S/N + D" After the "FFT" function is executed, this indicator box displays the result of the calculation of signal-to-noise plus distortion with respect to the fundamental, of the active data array. * "S/D" After the "FFT" function is executed, this indicator box displays the result of the calculation of signal-to-distortion with respect to the fundamental, of the active data array. DS458DB1A2 CDB5451-1 * "SAVE To File" Clicking on this button will save the data that is plotted in the graph window to a text file. A pop-up window will appear which prompts the user to specify a path and file name to which the data will be stored. should not be set to less than 275. Errors may occur in the rms and energy calculations if this value is less than 275. * "# of R-T Samples to Collect" This box is used to set the number of computation cycles to calculate before stopping the realtime sequence. For example, suppose that this box is set (by the user) to a value of 200, then real-time will run for 200 computation cycles, and then it will stop on its own. If the value of this box is set to -1, then real-time will run continuously or until the user turns real-time off by mouse-clicking on the "Real-Time Capture" switch. * "Real-Time Samples Count" This indicator box displays the number of computation cycles that have elapsed/transpired since the "Real-Time Capture" switch was set to the "On" position. * "RMS Voltage" Displays the result of the latest rms calculation for the voltage samples. This box will be updated after each computation cycle. Note that the scale of the values in this box are based on a normalized scale, where the maximum value is +1 and the minimum value is -1. Note that to obtain a value of +1 in this box, the user must set the voltage level to the CS5451's voltagechannel inputs to a DC level that is equal to the full-scale input level of the CS5451 (800mV). (Actually the maximum possible value is just less than +1, more like 0.9999... and the minimum value is -0.9999...) * "RMS Current" Displays the result of the latest rms calculation for the current samples. This box will be updated after each computation cycle. Note that the scale of the values in this box are based on a normalized scale, where the maximum value is +1 and the minimum value is -1. A value of +1 19 3.2.6 Real-Time Mode The real-time functions are located in the top-right corner of the Data Panel. Real-Time allows the user to calculate the rms values of the current and voltage signals from one channel pair. Note that this mode can only be run on one of the three channel pairs at a time. The user must select which channel pair is to be analyzed, by manipulating the "Channel Pair Selector" switches on the right-hand side of the Data Panel. In addition to rms calculation, the energy is calculated as well. Each instantaneous pair of voltage and current samples is multiplied together, and these voltage-current product terms are summed together to create the energy reading. * "Real-Time Capture" Setting this switch to the "On" position will initiate the real-time data collection sequence. To end the real-time sequence, change the switch back to the "Off" position (using the mouse). * "Cycle Count" This box is used to set the duration of the computation cycle. The computation cycle is defined as the number of samples over which the rms and energy calculations are performed. If this box is set to 4000, then the rms and energy results will be updated every 4000 samples. If the sampling frequency is at 3906 Hz, one computation cycle lasts for ~1.024 seconds. The value in this box sets the number of samples to use for one computation cycle. This box can be modified by the user. The larger the value of the computation cycle, the more accurate the rms results will be. The computation cycle DS458DB1A2 CDB5451-1 is obtained in this box is obtained by setting the CS5451 current-channel input voltage to a DC level that is equal to the full-scale input level of the CS5451. (Actually the maximum value is just less than +1, more like 0.9999... and the minimum value is -0.9999...) * "Energy" Displays the results of the latest energy calculation. The energy calculation is obtained by summing the most recent N voltage-current product terms, where N is the value in the "Cycle-Count" box. * "Save Real-Time To File" Clicking on this button (with the mouse) will allow the user the save the results of the most recent real-time sequence to a file. The user will be prompted for a path and filename to which the results will be saved. The CS5460A serial interfaces are SPITM and MicrowireTM compatible. The interface control lines (CS, SDI, SDO, and SCLK) are connected to the 80C51 microcontroller via port one. To interface an external microcontroller, these control lines are also connected to HDR6 (Header 6). However to accomplish this, the evaluation board must be modified in one of three ways: 1) cut the interface control traces going to the microcontroller, 2) remove resistors R4, R7, R8, and R13, or 3) remove the microcontroller. . 20 DS458DB1A2 CDB5451-1 Figure 7. Silkscreen DS458DB1A2 21 CDB5451-1 Figure 8. Circuit Side 22 DS458DB1A2 CDB5451-1 Figure 9. Solder Side DS458DB1A2 23 CDB5451-1 4. ADDENDUM 4.1 Errata for CDBCAPTURE+ Recently the CDBCAPTURE+ board was updated with one additional 120 pF capacitor between the CKOUT line and the /IRQA line. This addition improves noise problems on the board. Figure 10 is a diagram which illustrates where this capacitor needs to be placed, in case the user has an older version of the CDBCAPTURE+ board. The user should add this capacitor to the board if it is not there already. R24 CKOUT R9 120 pF /NMI R10 /IRQB R11 /IRQA To eliminate noise (from PLD) on IRQA, Solder ~120 pF cap as shown. Figure 10. Recent ECO to CDBCapture+ Board 24 DS458DB1A2 * Notes * |
Price & Availability of CDB5451-1
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |